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Design
for Testability and for Built-In Self Test |
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 What
you will learn:
In this course you will learn all aspects of Design for Testability, from what it is, why you might need it, why someone would object to it, and what it can and cannot accomplish. You will learn how today's technology has become elusive to certain failure modes and how important it is to expose them through more testable designs. First you will learn some simple techniques to enhance observability and controllability. You will learn how you can access literally hundreds of internal points with as few as four additional edge connector pins. You will learn specific guidelines for both digital and analog circuit testability. You will learn structured testability techniques, such as internal and boundary-scan. You will come away with a deep understanding of the IEEE 1149.1 (JTAG) standard's operation, use and even its limitations. You will also learn some new techniques in testability, including IDDQ testing and I/O Mapping. In the second part of the course, you will learn what built-in [self] test (BIST) is and how it can be specified. You will learn structures such as linear feedback shift registers (LFSRs), signature analyzers, and pseudo-random signal generators. With these building blocks you will be able to evaluate a number of BIST architectures. You will learn BIT Software techniques and consider the effect false alarms have on BIT. You will finally be able to specify BIT for your products and look at the possibilities of BIT taking over some of the ATE functions. Abstract: This is really two courses combined into one. The first part, Design for Testability provides the guidelines necessary to improve circuit design from a test perspective. It includes simple and easy-to-implement ad-hoc testability guidelines. Then the course looks at more sophisticated structured approaches to testability that can be placed into ICs and boards. Special emphasis will be given to boundary-scan, the (JTAG) IEEE-1149.1. This standard, which is often difficult to understand, will be made crystal clear. Analog circuit testability builds on the IEEE-1149.1 and is now the Mixed-Signal testability standard, designated as IEEE-1149.4. We examine this standard as well. A standard also exists to access board-level boundary-scan at the systems level. This is accomplished using the IEEE-1149.5, which we will also introduce. The second part of the course will cover Built-In Test. Starting with classification of Built-In Test approaches, the course introduces the building blocks of built-in self test (BIST) architectures. The course then examines some of these architectures, including Random Test Socket (RTS), the Built-In Logic Block Observer (BILBO), the Cyclic Analysis Testing Systems (CATS), the Built-In Test Exerciser and Sensor (BITES), and others. BIT software is also covered and a discussion on BIT false alarms is included. Finally, a hierarchical approach to BIT is examined, which offers a reduction if not elimination of ATE in both a manufacturing and maintenance environment. Who should Attend: This is a design course, intended for designers and for those who motivate them for testability, namely test engineers. Managers concerned with testability issues will also find this course useful. Anyone interested in boundary-scan (JTAG/IEEE-1149.1) will agree with many of our graduates who called this the best course available on the subject. Since Built-In Test is becoming an issue of concern for top management as well as to marketing, this course - though a bit on the technical side - does examine applications for BIT in a product. DESIGN FOR TESTABILITYPart 1 - Introduction to Design for TestabilityWhat is Design for Testability? Quality As a Function of Yield and Test Coverage Fault Models Effect of Time-to-Market On Profits Technical Goals of Testable Designs Considerations for Testability Approaches to Design for Testability
Design for Testability Attributes
Basic Ad Hoc Design for Testability Rules Controllability
Observability I/O Amplification Predictability Partitioning to Functionally Independent Sub-Systems
Methods for Breaking Feedback Loops Breaking Long Counters and Shift Registers Methods for Breaking Free Running Clocks Part 2 - Application of Testability GuidelinesProgrammable Logic Arrays (PLAs) Testability Guidelines ASIC DFT Guidelines Analog Testability
LSI, VLSI, V2LSI, GSI, VHSIC Testability Guidelines Mechanical Design for Testability Guidelines for Surface Mount Devices Schematic Drawings Documentation for Testability Testability Problems With Memories Cross-Check I/O Mapping IDDQ Testing
Evaluating Designs for Testability
Part 3 - Structured Design for TestabilityTechnical Goals of Testable Designs General Structure of Scan Scan Design Mode of Operation
Boundary Scan Structure The Boundary Scan Cell and JTAG/IEEE-1149.1 Construction Of The Test Access Port (TAP)
Boundary-Scan Registers Boundary-Scan Operational Modes
Boundary-Scan Description Language (BSDL) Boundary-Scan Tests
Mixed Signal Boundary Scan Using the IEEE-1149.4 AC EXTEST Using the IEEE-1149.6 Evaluating Designs for Testability Built-In Self TestPart 1 - Technical Approach to BISTForms Of Built-In Test
Elements of a BIST Architecture Types of BIST BIST Classification BIT Using Error Detection Codes Error-Correcting Codes BIT Using Set/Scan Logic
BIST Signal Generation tools Test Generation Methods for BIST BIST Response Collection tools BIST Architectures
BIT and BITE Architectures
General Structure Of Non-Concurrent Bit Part 2 - BIT SoftwareWhy use BIT Software? BIT Software Considerations
Failure Analysis Software
Evaluating BIT Basic BIT and BITE Requirements Self Checking BIST BIT False Alarms
BIT Specification Manufacturing Test Strategies with Hierarchical BIT Maintenance Test and Repair Strategies with Hierarchical BIT What happens to ATE? See
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