WebCourse - Design for Testability 501 - Advanced DFT Techniques

What you will learn:

Boundary Scan pioneered a new approach to testability for board level. It is, however, important to integrate this with other forms of assembly. For today's complex circuits it may not be sufficient to test the boundary of the IC. Rather we will need to test inside the IC even when the IC is already mounted on a circuit board and when that board is already part of a module or system. This webinar will teach you about newer tools and the integration of those tools with traditional testability approaches.

Abstract:

While Boundary Scan served the digital board test, a need exists to handle analog circuits, using IEEE-1149.4, AC coupled circuits using IEEE-1149.6, and JTAG approaches within the IC using IEEE-1149.7. In this webinar we explore these and other standards or preliminary standards to increase the power of testability and further reduce the cost of test.

Who should attend:

This more advanced webinar is intended for those who have attended the other four in this series or who have the background to tackle these topics.

Detail:

Design for Testability DFT 501 - Advanced DFT Techniques

The following topics will be explored in this webinar:

Where Boundary Scan Stops
- Historical Developments
Analog and Mixed Signal Boundary Scan Using IEEE-1149.4
AC Coupled Bounday Scan Using IEEE-1149.6
In System Programming Using IEEE-1532
Connectivity of Non-Boundary Scan Devices Using IEEE-P1581
Reduced Pin Count TAP Using IEEE-1149.7
Analog Toggle Using IEEE-1149.8
Internal JTAG Using IEEE-P1687
System Level Test Using SJTAG
- eXternal Boundary Scan Test (XBST)
- Embedded Boundary Scan Test (EBST)
Other Testability Approaches
- I/O Mapping
- IDDQ Testing
The future of Testability
- Testability and Built-In Self Test
- Testability and Built-In Self Repair

This is the fifth of a series of Webinars on the subject. Others, presented in consecutive lectures include:
   DFT 101 - Who, What, When, Why, How Much?
   DFT 201 - Techniques for ICs, Boards and Systems
   DFT 301 - JTAG/Boundary Scan/IEEE-1149.1
   DFT 401 - System Level Testability and Diagnosability

Instructor: Louis Y. Ungar

Louis Y. Ungar is president of A.T.E. Solutions, Inc., a leading independent test and testability consulting and educational firm. He has taught ATE and Testability courses at the University of California at Los Angeles (UCLA) and throughout industry. Mr. Ungar is a consultant to The American Society of Test Engineers, has served as Testability Chair for the Surface Mount Technology Association and has served on committees for various IEEE standards, including those of IEEE Std. 1149.x. Mr. Ungar holds a B.S.E.E. and Computer Science degree from the UCLA and has completed his course work towards a M.A. in Management.

Availability:
Format	Date	Length	Location	Price
Webinar	7-16-10	1.5 hour webinar	WebCourse Start - 10 AM Pacific, 1 PM EST, 18:00 GMT	$199.50
Onsite		1.5 hour webinar	On Demand	$599.50