VLSI Simulation and Test Generation

What you will learn:

The stuck-at models used in simple logic is becoming obsolete when we wish to test Very Large Scale Integrated circuits. You will learn new approaches to test that can be used to test highly complex circuits.

Abstract:

The course introduces simulation, test pattern generation - both manual and automatic. It also covers memory testing.

Who should attend:

Anyone who deals with tests of complex VLSI and Application Specific ICs (ASICs) will find this course important.

Detail:

COURSE OUTLINE:

Introduction

Economics of VLSI Failures
Test Definition of Combinational and Sequential Circuits
Microprocessors and Programmable Logic

VLSI Tests

Parametric Tests
Time Dependent Faults
Stuck-at Faults
Fault Coverage

VLSI in Boards and Systems

Fault Detection
Fault Isolation and Resolution
Guided Probing
Probe Technology & Expert Systems

Memory Testing

Effects of Memory
Timing Analysis
Memory Tests

Simulation

Purpose of Simulation
Hierarchical Simulation
Fault Simulation Methods

Automatic Test Pattern Generation (ATPG)

The D-Algorithm
Critical Path and LASAR
PODEM and FAN
Boolean Differences
The Subscripted D-Algorithm

VHSIC Hardware Description Language (VHDL)

Introduction to VHDL
Functional Fault Model
Heuristics for Sequential Tests

System-On Chip

What is a SOC?
SOC Fault Detection and Fault Diagnosis
Design for Testability issues in SOC
SOC and Built-In Self Test
SOC Test Programming

Availability:
Format	Date	Length	Location	Price
ConsulTraining				RFQ
CourseNotes				RFQ
Onsite				RFQ
Private			Los Angeles	RFQ