What you will learn:
The Testability Director will enable you to design circuits which are testable. The guidelines are provided as you design and you can evaluate your design's testability before you finalize it and before costs of design changes make testability prohibitive.
Abstract:
The Testability Director is a spreadsheet template, which guides in the development of testable designs. It contains the Inherent Testability Checklist used with MIL-STD-2165, the U.S. Government's Testability Program for Electronic Systems and Equipments. But Version 3.2 goes much further, bringing you hundreds of guidelines from IC design through board and system testing. It includes guidelines for X-ray and Automated Optical Inspection. It also includes fixturing guidelines for bed-of nails, flying probe and even vectorless test approaches.
Detail:
The Testability Director will give you an Overall Testability Score in various aspects of circuit design. What you will get is a report similar to the one below:
Overall Testability Score Sheet and Section Weight Assignment
| |
|
Assigned Section Weight |
Section Score in Percent |
Section Weight |
Section Weighted Score |
| G00000 |
General Guidelines |
10 |
12% |
720.0 |
86.4 |
| I00000 |
IC and ASIC Level Testability Guidelines |
|
|
|
|
| I10000 |
VLSI, ASIC and Microprocessor Circuit Guidelines
|
8 |
80% |
1368.0 |
1098.1 |
| I30000 |
Memory and Programmable Circuit Guidelines
|
6 |
85% |
450.0 |
383.5 |
| I50000 |
Structured Design for Testability Guidelines
|
9 |
62% |
432.0 |
266.2 |
| B00000 |
Board Level Testability Guidelines |
|
|
|
|
| B10000 |
Inspection
|
|
|
|
|
| B11000 |
Automatic Optical Inspection Guidelines
|
6 |
78% |
480.0 |
373.7 |
| B13000 |
Automated X-Ray Guidelines
|
8 |
86% |
320.0 |
240.5 |
| B30000 |
Connectivity Guidelines |
|
|
|
|
| B31000 |
Flying Probe Connectivity Guidelines
|
6 |
93% |
102.0 |
94.8 |
| B33000 |
Vectorless Test Guidelines
|
7 |
81% |
259.0 |
208.6 |
| B35000 |
Boundary-Scan Connectivity Guidelines
|
9 |
76% |
99.0 |
75.4 |
| B50000 |
In-Circuit Board
Testability Guidelines |
|
|
|
|
| B51000 |
In-Circuit Test and Testability Guidelines
|
8 |
89% |
1712.0 |
1522.9 |
| B53000 |
Boundary-Scan In-Circuit Testability Guidelines
|
8 |
77% |
352.0 |
271.3 |
| B70000 |
Functional Board Test and
Testability Guidelines |
|
|
|
|
| B71000 |
Digital Circuit Guidelines
|
7 |
93% |
1575.0 |
1460.7 |
| B73000 |
Analog Circuit Guidelines
|
5 |
88% |
325.0 |
285.8 |
| B75000 |
Board Level Boundary-Scan and BIT Guidelines
|
7 |
88% |
630.0 |
552.4 |
| S00000 |
System Level Testability Guidelines
|
|
|
|
|
| S01000 |
General System Level Guidelines
|
8 |
85% |
640.0 |
543.8 |
| S03000 |
System Level BIT Guidelines
|
8 |
89% |
952.0 |
850.3 |
| |
Totals |
|
|
10416.0 |
8314.2 |
| Overall Testability Score |
|
80%
|
|
|
