Design for Excellence

  Design for Excellence (DfX)
 Bringing all the –ilities together

Monday

Introduction

What Constitutes DfX

Reliability
Safety
Electromagnetic Compatibility
Usability
Testability
Built-In SelfTest
Manufacturability
Maintainability
Diagnosability
Others

Failure Mode Effects Analysis (FMEA)

A Common Platform for all the -ilities

Design and Test for Electromagnetic Compatibility

Tuesday

Design for Reliability

New paradigms in design for reliability

Designing products for long life

Design FMEA for avoiding failures

Accelerated life testing models

Weibull analysis for life test data

Design for Safety

Evidence-based safety design methods

Hazard analysis and risk mitigation techniques

Active safety vs. passive safety

Testing for safety

Wednesday

Design for Manufacturability

Customer Satisfaction Requirements
Functional Responsibilities of DFM
Concurrent Engineering
Early Supplier Involvement
Defining the Process
Six Sigma and Statistical Thinking
Understanding and Controlling Process Variation
Understanding and Implementing a World Class Quality System
Process Characterization Concepts
Evaluating Printed Circuit Board Designs
The "Black Belt" Quality Certification Program
    Improve Process Availability and Yield
    Use of Process FMEA to reduce vulnerability in manufacturing
    Reliability centered maintenance

Thursday

Design for Usability

      Usability Terms
      Usability Engineering
      Usability Documentation
      Usability Measures
      False Alarms – A consequence of poor usability

Automatic Testing and ATE Strategies

Design for Testability

            What is Design for Testability?
            Quality as a Function of Yield and Test Coverage
            Fault Models
            Effect of Time-to-Market On Profits
            Approaches to Design for Testability
                        Ad Hoc Design for Testability 
                        Structured Design for Testability
                        Extended Design for Testability Or Built-In Self Test
            Design for Testability Attributes
                        Controllability 
                        Observability 
                        Others 
            Evaluating Designs for Testability
                        Dependency Models
                        Testability Checklists 
                         PCOLA/SOQ
                        Other Testability Analysis tools 
            Structured Design for Testability
            Technical Goals of Testable Designs
            General Structure of Scan
            Boundary Scan Structure (JTAG/IEEE-1149.1)
            Boundary-Scan Operational Modes
                        Non-Invasive Operational Modes 
                        Pin Permission Operational Modes
            Boundary-Scan Description Language (BSDL)
            Boundary-Scan Tests
            Mixed Signal Boundary Scan - IEEE-1149.4
            AC EXTEST Using the IEEE-1149.6
            Other Testability Guidelines and Organizations
                        SMTA Testability Guidelines
                        Testability Management Action Group (TMAG)
                        IEEE-1149.7 and beyond..

Friday

Design for Built-In Self Test

            Technical Approach to BIST
            Forms of Built-In Self Test
                        Continuous Monitoring (CM)
                        Initiated Bit (I-BIT) 
                        Operational Readiness Test (ORT)
            Elements of a BIST Architecture

            BIST Classification

            BIST Using Set/Scan Logic
                        Signature Analyzer 
                        Pseudo-Random Signal Generator

                        Linear Feedback Shift Register from Scan Cells 
                        Built-In Logic Block Observer (BILBO)

            BIST Signal Generation tools

            BIST Response Collection tools
            BIST Architectures

            Built-in Test (BIT) Software

            Why use BIT Software?

            BIT Software Considerations
                        Guidelines for Software BIT 
                        Selecting a Software Language 
                        Performance Monitoring Software

            Failure Analysis Software
                        Fault Filtering 
                        Heuristics in BIT
            BIT False Alarms

            Evaluating BIT

            BIT Specification

Design for Maintainability

            MIL-HDBK-470A
            The Support Concept –
                   Design for Operational Readiness
            Preventive vs. Corrective Maintenance
             Human Engineering
           Design for Maintainability Requirement  
            Interaction between Human and Product
                   Design choices of switches, knobs, levers, wheels, etc.
                   Anthropometrics 
             Testability in Maintenance
            Diagnostics in Maintenance
            Built-In Test in Maintenance
             Prognostic
            Maintainability Analyses
                   Equipment Downtime Analysis
                   Maintainability Design Evaluation 
                   Failure Mode Effects Analysis (FMEA)
                   Testability Analysis
                   Human Factors Analysis

Design for Diagnosability

Other –illities

Bringing it All Together Under a Single Common Criterion

Louis Y. Ungar, President, A.T.E. Solutions, Inc.

Louis Y. Ungar founded A.T.E. (Advanced Test Engineering) Solutions, Inc. in 1984 and built it to be the leading independent testability consulting and educational firm. He has taught ATE, Testability and Built-In Self Test courses at the University of California at Los Angeles (UCLA) and throughout industry and governments.  Louis is also the founding President of the Testability Management Action Group (TMAG), a consultant to The American Society of Test Engineers (ASTE), has served as Testability Chair for the Surface Mount Technology Association (SMTA) and has served on committees for various IEEE standards, including those of IEEE Std.1149.x.  He has widely published on Design for Testability and Diagnosability topics and obtained patents for Built-In Self Test circuits.  Mr. Ungar holds a B.S.E.E. and Computer Science degree from UCLA and has completed course work towards a M.A. in Management.

Dr. William Duff, President, SEMTAS Corporation

Bill received a BEE degree from George Washington University in 1959, a MSEE degree from Syracuse University in 1969, and a DScEE degree from Clayton University in 1977. Bill is a founder and President of SEMTAS and is internationally recognized as a leader in the development of engineering technology for achieving electromagnetic compatibility (EMC) in communication and electronic systems.  He has 42 years of experience in EMC analysis, design, test and problem solving for a wide variety of communication and electronic systems.  Bill has developed and applied EMC analysis, modeling and simulation techniques for evaluating EMC within and between communication and electronic systems operating in severe electromagnetic environments. The models were developed for Rome Air Development Center (RADC). The models were also used by the US Navy for “topside design” of ships and are  used to evaluate EMC and determine antenna separation requirements for various types of civilian and military communication systems that are collocated on towers, rooftops, ships, aircraft, vehicles, etc.    Bill has written more than 40 technical papers and four books on EMC.   He is a past president of the IEEE EMC Society and a past IEEE Director of Division IV, Electromagnetic and Radiation.  He has served a number of terms as a member of the EMC Society Board of Directors and is currently Chairman of the EMC Society Fellow Evaluation Committee and an Associate Editor for the EMC Society Newsletter.  Bill has received a number of IEEE awards including the Lawrence G. Cumming Award for Outstanding Service, the Richard R. Stoddard Award for Outstanding Performance and a “Best Paper” award.  He was elected to the grade of IEEE Fellow in 1981.  He is a NARTE Certified EMC Engineer.

Joe Belmonte, Principal Consultant, ITM Consulting

Joe has been a process engineer and process engineering manager in the electronic manufacturing industry for over 30 years with experience in all aspects of electronic product assembly operations.  He holds an Associate Degree in Mechanical Design from Wentworth Institute in Boston and a Bachelor of Science Degree in Operations Technology from Northeastern University in Boston . From 2007 to 2009 he worked at Bose Corporation as the Manager of Advanced Manufacturing Engineering and as a Supplier Engineer and was responsible for the development and implementation of all new electronic manufacturing processes at Bose Manufacturing Operations and the training of all Bose Electronic Manufacturing/Process Engineers.  From 1995 to 2007 Joe was a Consultant at Cookson Electroics/Speedline Technologies Performance Solutions Group and Project Manger at Speedline Technologies Advanced Process Group where he worked with customers on quality and cycle time improvement projects including performing detailed assessments of their entire manufacturing operation to identify strengths and opportunities for improvement.  As Project Manager at Speedline Technologies Joe’s primary responsibilities included managing advanced process development projects (Lead Free Process Development Program, High Volume Fuel Cell Process Development Program, and Miniature Component Assembly Process Development), working with customers on process improvement programs, and providing process training.  From 1978 to 1995, Joe worked as a process engineer and process engineering manager at Motorola ISG .  Joe has been a senior member of the Society of Manufacturing Engineers (SME) for over 20 years, has served as a member of the Electronic Manufacturing Association of SME Board of Advisors and currently serves as a member of the SMTA Board of Directors.

Dev Raheja, President, Design for Competitiveness

Dev G. Raheja, is a world leader in reliability engineering with over 30 years experience as an educator, innovator, author, practitioner and consultant. He has done consulting and training for automotive, aerospace, defense and many high tech corporations. Mr. Raheja is credited with turning around two U.S. manufacturing companies from going out of business to achieving No. 1 market leader position. His prior affiliations include: senior management consultant responsible for risk management and system assurance at Booz-Allen & Hamilton, Inc.; Chief Engineer for corporate product reliability and safety at Cooper Industries; manager of manufacturing engineering, and quality assurance at GE; and Design Engineer at Standard Screw Company. He has received several awards including the ASQ Austin Bonis Reliability Education Advancement Award. He has chaired several technical committees; ex-chairman of EIA Software Reliability sub-committee and the Ultra High Reliability Engineering Committee of Aerospace Industries Association and the SAE G-11 Committee. Mr. Raheja is author of the book  Product Assurance Technologies: Principles and Practices  and He has also served as the Adjunct Professor at the Graduate School , University of Maryland for its PhD program on reliability engineering. He serves on the AIAA S-102 R&M Standards Working Group to develop standards on Dependability, Operational Availability, Software Reliability and related standards. He is the Chairman of IEEE Design for Reliability Committee.