Design for Testability Consulting

Design for Testability is one of the most cost-effective ways of tackling test problems. 

It is only effective, however, if it is performed properly and at the proper time. 

We can work with your

• managers to develop guidelines, 
• designers to provide on-the job consulting, and 
• test engineers to help evaluate and implement testability requirements. 

We have expertise with the

• JTAG/IEEE 1149.1 boundary-scan, 
• IEEE 1149.4 Mixed Signal boundary-scan
• IEEE-1149.5 System Level Bus, 
• MIL-STD-2165 US Navy's Testability Standard,
• British Standard 013 Design for Testability Guidelines,
• Surface Mount Technology Association Testability Guidelines TP-101C 2002

Our engineers were involved with the standardization of IEEE 1149.5 and IEEE 1149.4.  We were one of the first to produce Testability Analysis Reports approved by the US Navy and are active in bringing about other testability standards.  We have also helped a number of commercial companies profit from lower overall test, repair and bad product delivery penalty costs, by making their designs more testable. 

In 2002 Louis Ungar led a team of world-wide industry experts to develop the Surface Mount Technology Association's Testability Guidelines.

To assist in our consulting, we utilize The Testability Director software, that scores the inherent testability of a design at the chip (ASIC), board and system levels. 

If we can be of assistance, write to LouisUngar@ieee.org or call (310) 822-5231